Accepted Papers for Symposium E

  • High Throughput and Low power 64 point Feed forward FFT Processor
    Sarada V*, SRM University

  • Characterization of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications
    Maria Jossy*, SRM Univeristy; Vigneswaran T, VIT University

  • Design and Analysis of Memristor Based 12T SRAM Cell for low Power application
    Radhika selvam*, SRMUniversity

  • Stochastic LU Decomposition Scheme for MIMO Receivers
    Nitin gurjar*, srm university

  • Front-End CMOS Circuit for Low Power Consumption
    dinesh kumar*, SRM University

  • Smart cache memory management on divider machine
    Saurav Sarkar*, National Institute of Technology Nagaland

  • A Parallel Pipelining VLSI Architecture of Lifting Based 3-D Discrete Wavelet Transform
    Prethippa M*, valliammai engineering college; Dr.Usha N, SRM Valliyammai College of Engineering

  • A Preliminary Study of Oscillators, Phase and Frequency Detector and Charge Pump for Phase Locked Loop (PLL) Applications.
    Prithiviraj R*, SRM university; selvakumar J, SRM university

  • VLSI Implementation of Adaptive Low Power Noise Cancellation for broadband portable audio devices
    A R saiprasad*, SRM University; Selvakumar J, SRM university

  • Design and Implementation of Thermally Actuated Latching Mems Switch for Replacing Electromagnetic Relays in Telecommunication Application
    Kamaladevi R*, Aalim Muhammed Salegh College of Engineering

  • Design and analysis of a millimeter wave fractional N frequency synthesizer
    Parvathy P*, SRM university; N saraswathy, SRM university

  • All digital RF Transmitter with highly power efficient Doherty Power Amplifier
    Deepa Pradeep*, SRM university; B Ananda venkatesan, SRM university

  • Design and Analysis of High Efficiency Doherty Power Amplifier for Broadband applications
    Rupali Singh*, SRM University

  • Low Noise and High Gain Low Noise Amplifier for 76–77 GHz long-range and 77–81 GHz short-range automotive radars
    Nitesh Verma*, SRM University

  • Adiabatic Techniques for Energy Efficient Barrel Shifter Design
    Anantharaman K*, SRM University

  • Leakage Power Reduction in CMOS VLSI Circuits by Three Step-Wake Up
    Dorathy sylvia*, Easwari Enginerring College; Jessintha Kumar, Easwari Engineering College

  • A Short review:VLSI MSV Floorplanning
    Srinath B*, SRM IST; Gigin R, SRM IST ; Soumya Garg, SRM IST; Arunapriya s, SRM IST

  • A 79GHz CMOS LNA with Adaptive Biasing
    Rubeena Dudekula *, SRM University ; J Manjula, SRM University

  • Analytical Modeling of Gate Engineered Triple Material Gate (TMG) AlGaN/GaN High Electron Mobility Transistors for CMOS Applications
    Venkatesh M*, Thiagarajar College of Engineering; Dr.Balamurugan .N.B, Thiagarajar College of Engineering

  • X-Band Phased Array Transmitter in 180nm SiGe BiCMOS Technology with Stacked Power Amplifier
    Sijo thomas*, SRM university; T saminathan, SRM university

    Sarathy Govindarajan*, SRM University

  • Performance analysis of Eight Port Octagon Structure based Circuit Switching
    Karthi keyan*, PSNA CET

  • Design and Implementation of FPGA based 64 bit MAC unit using VEDIC Multiplier and Reversible Logic gates
    Siva Nagendra Reddy*, Kuppam Engineering College

  • An Efficient Blind Detection Watermarking Algorithm Using Range Conversion Method
    Muthu shanmugam*, rmk college of engineering and technology

  • Performance analysis of Trace Forward based Viterbi Decoder
    Azarudeen m*, psna cet

  • Performance analysis of MUX based convolutional encoder
    Mano p*, psna cet

  • Novel Adaptive Reconfiguration Algorithm based high reliable signal processing for software defined radio
    Deepa Jose*, KCG College of Technology

  • A New High Speed Multiplier based on Carry Look Ahead Adder and Compressor
    Jeevan B*, KITS, Warangal; Sivani K, Kits, Warangal

  • Performance Analysis of King Topology Using Routing Technique
    Madhu bala*, PSNA CET

  • A Smart Prioritized Ambulance Service Using Mobile ZigBee in a Traffic Control System
    Naveena K*, PSNA CET

  • Design and Verification of ACK NAK Protocol of PCI Express Data Link Layer in System Verilog
    Gokulakrishnan S*, Easwari Engineering College

  • Lesion Segmentation of Brain with The Tumor & Stroke
    Manju V*, PSNA College of Engineering and Technology

  • Real-time Automatic Peaks and Onsets Detection of Photoplethysmographic signals
    Madhan Mohan P*, sathyabama university; Nagarajan V, Adhiparasakthi engineering college; Vignesh J.C, Jasmin Infotech Pvt Ltd

  • Design of Low Power CMOS Four Quadrant Analog Multiplier in Nano Meter Scaling
    Sharath N*, SRM University

  • Design and Implementation of ADPLL for Digital Communication Applications
    Abhishek Chaudhary*, NIT Manipur; manoj kumar, NIT Manipur

  • Design and Analysis of On-Chip Low Power, Low Drop-Out Voltage Regulator Using FFRC AND MCC Technique
    komal nagda*, GITS,udaipur

  • Resolvement of Power Quality Problems by Unified Power Quality Conditioner (UPQC)
    Rohini Dabhade*, SND COE & RC YEOLA

  • Enhanced Area and Delay Efficient Carry Skip Adder
    Kumaran Karmegavannan*, Manakula Vinayagar Institute of Technology; Anantha Bhanumithra.G, Manakula Vinayagar Institute of Technology; Rathi Rajamony, Manakula Vinayagar Institute of Technology; Mohana Priya.M, Manakula Vinayagar Institute of Technology

  • A Differential Active Inductor Based High Linearity Wideband Common Gate Low Noise Amplifier ,Using Common Drain Topology for Impedance Matching
    Pratitee Chattopadhyay*, SRM University

  • Designing embedded Dram cells for ultra low power low voltage application
    snigdha chandrika*, SRM University

  • Weak Cell Detection Techniques for Memristor Based Memories
    Ravi V*, VIT University Chennai Campus; Prabaharan SRS, VIT University, Chennai Campus

  • Design and Implementation of Multi-Bit Self-Checking Carry-Select Adder
    Shivkumar Kavitkar*, VIT University, Chennai; Anita Angeline A, VIT University Chennai Campus; Kanchana Bhaskaran, VIT University, Chennai

  • Memristor based Approximate Adders for Error Resilient Applications
    Muthulakshmi S, VIT University Chennai Campus; Chandra Sekhar Dash, VIT University, Chennai Campus; Prabaharan SRS*, VIT University, Chennai Campus

  • Performance Analysis of Semi Supervised Approach in Dental Field
    Sheeba M*, PSNACET

  • Cross Talk Rejection of Silicon Piezoresistive Acceleration Sensors
    vetrivel sankar, VIT University; Ravi Sankar*, VIT University

  • Impact of Varying Lateral Straggle Length At Source/Drain of Underlapped Double Gate Nmosfet
    Venishkumar T*, Sethu Institute of Technology

  • Performance of 77GHz double balanced up conversion mixer for Autonomous cruise control RADAR in 180nm CMOS
    Nishant Ingole*, SRM University

  • A Novel Method for Design and Implementation of Low Power, High Stable SRAM cell
    Ashish Sharma*, VIT University; Ravi V, VIT University Chennai Campus

  • Development of UVM based Reusable Verification Environment for UART with APB Interface
    oshin mehta*, VIT university

  • An Energy Aware Mass Memory unit for small satellites using Hybride Architecture
    Khaled AOURRA*, Beijing institute of technology

  • Optimization of Power in Low Power VLSI Design using a Novel Adiabatic Logic Circuit Designed using FinFET
    BHUVANA B P*, VIT University; Kanchana Bhaaskaran V S, VIT University Chennai

  • An ASIC Based Image Watermarking of Grayscale Images Using Pipelined 2d Integer DWT
    Sakthivel S M*, VIT University; Ravishankar A, VIT University, Chennai

  • Test Signal Generation for Detecting Faults on Mil-std 1553 bus
    Sowmya Madhavan*, Nitte Meenakshi Institute of Technology

  • Low Cost Detection of Metal Ions Concentration in Water
    Manoj Veluri, Amrita University; Manohar korupolu, Amrita University; Deepa Shenoy, Amrita University; Sujadevi V G*, Amrita Vishva Vidyapeetham, Amrita University; Prabaharan P, Amrita University

  • Adiabatic Sram Cell and Array
    Ayon Manna*, Vit university chennai

  • VLSI Aspect of AES S-box Based on Finite Fields.
    Abhimanyu Rajemane*, VIT University chennai

  • Integrated MEMS Capacitive Pressure Sensor with On-Chip Cdc for A Wide Operating Temperature Range
    Y Sai Charan*, VIT University; Ananiahdurai S, VIT University

  • Retiming approach to enhance the throughput of Advanced Encryption Algorithm [AES] in Field Programmable Gate Array [FPGA].
    Moksha Ojha*, VIT University

  • Performance Analysis of Low-Power Parallel Sampling Tdc with Power Gating and Dem In 45-Nm Cmos
    Saraniya Umapathy*, VIT University; Lakshmi B, VIT Chennai

  • Design of a Hardware lock using Reversible logic
    Gunajit Kalita*, Assam Engineering College

  • A High SNDR and Wider Signal Bandwidth CT ∑∆ Modulator with a Single Loop Non-linear Feedback Compensation
    chandra sekhar*, VIT University Chennai

  • Design of Ultra Low Voltage- Energy Efficient Hybrid Full Adder circuit
    Basha M.Mehaboob*, SVR Engineering college

  • Performance Analysis of GDI Logic in Near Threshold Region: Case-Study of 10T Full Adder Circuit
    Kishore Sanapala*, VIT University, Vellore; Sakthivel R, VIT University

  • A comparative performance analysis of CAMs using different model files in Spice
    Tasneem Salam*, College of Engineering and Management Punnapra

  • Inexact multipliers for error resiling applications.
    Priya dharshni*, VIT university

  • Design of Current Mode CNTFET Transceiver for Bundled Carbon Nanotube Interconnect
    Murugeswari P*, theni Kammavar Sangam College of technology; Kabilan A.P., Madanapalle institute of technology and science,; Jayanthi VE, PSNA College of Engineering and Technology

  • An efficient design of Decoder circuits in coplanar quantum-dot cellular automata
    Mohit Kumar*, NIT Kurukshetra

  • MTCMOS based Soft Start Circuit for Low Leakage LED Driver with Minimum In-Rush Current
    Magesh Kannan Parthasarathy*,

  • Implementation of Dual-Hysteresis Mode Flip-Flop Multivibrator Using Differential Voltage Current Conveyor
    AMIT Bhattacharyya*, Haldia Institute of Technology,Haldia